Hour: From 15:00h to 18:00h
Place: Mir-Puig Seminar Room (MP210)
FPGA: Lectures for Scientists
FPGA Lectures for Scientist is a collection of hands-on FPGA programming lectures for scientists without (or very basic) experience in FPGA programming. The intent is to provide simple, functional and opensource examples, which incrementally incorporate new FPGA programming concepts. This course speeds up the initial learning curve and, after its completion, the attendees will be able to create their own FPGA designs that interface with digital & analog IOs.
Dates and Venue: 18th, 25th Of November and 2th and 9th and 16th of December from 15:00 – 18:00
Target Group: PhD students, Post-doctoral researchers and engineers with interest for high-speed digital electronics and who can benefit from custom signal generation and acquisition logic.
Available places: 10
Training content:
- VHDL/Verilog development
- Behavioral simulation
- Xilinx Zynq (FPGA chipset), Vivado (FPGA development environment), PYNQ (Python runtime configuration environment)
- Digital IOs
- Analog IOs (high-speed DAC / ADC)
- Advanced signal processing (DMA, DDS…)
Hour: From 15:00h to 18:00h
Place: Mir-Puig Seminar Room (MP210)
FPGA: Lectures for Scientists
FPGA Lectures for Scientist is a collection of hands-on FPGA programming lectures for scientists without (or very basic) experience in FPGA programming. The intent is to provide simple, functional and opensource examples, which incrementally incorporate new FPGA programming concepts. This course speeds up the initial learning curve and, after its completion, the attendees will be able to create their own FPGA designs that interface with digital & analog IOs.
Dates and Venue: 18th, 25th Of November and 2th and 9th and 16th of December from 15:00 – 18:00
Target Group: PhD students, Post-doctoral researchers and engineers with interest for high-speed digital electronics and who can benefit from custom signal generation and acquisition logic.
Available places: 10
Training content:
- VHDL/Verilog development
- Behavioral simulation
- Xilinx Zynq (FPGA chipset), Vivado (FPGA development environment), PYNQ (Python runtime configuration environment)
- Digital IOs
- Analog IOs (high-speed DAC / ADC)
- Advanced signal processing (DMA, DDS…)