Hour: From 12:00h to 13:00h
Place: Seminar Room
SEMINAR: Towards an active CMOS electronics-photonics platform based on subwavelength structured devices
As Moore's Law scaling faces fundamental bottlenecks, optical communication has emerged as essential for advancing computing performance through high bandwidth and energy efficiency. Silicon photonics, compatible with CMOS manufacturing, enables on-chip optical links but requires convergence with microelectronics to realize full potential.
This work leverages advanced monolithic electronic-photonic CMOS platforms (GlobalFoundries 45CLO) to demonstrate photonic crystal (PhC) nanobeam cavities with unprecedented performance metrics. We achieved the smallest footprint, largest intrinsic quality factor exceeding 100,000, and smallest mode volume yet demonstrated in any monolithic CMOS platform—the highest quality factor among fully cladded PhC nanobeam cavities in SOI platforms.
Two critical challenges historically limited PhC cavity adoption: demanding lithography requirements and integration complications in wavelength-division multiplexing (WDM) systems due to unwanted reflections. We address the integration challenge through a novel approach using paired PhC nanobeam cavities with opposite spatial mode symmetries, creating traveling-wave-like behavior that enables seamless WDM integration without reflections.
We present the first PhC modulator demonstration in a CMOS platform, featuring sub-wavelength contacts and reflection-less architecture. This concept extends to reflectionless microring resonator units, potentially optimizing modulation efficiency for interdigitated p-n junction designs.
Finally, we demonstrate non-invasive near-field scanning optical microscopy (NSOM) characterization of photonic devices within large-scale CMOS circuits using flip-chip post-processing, providing essential tools for future high-performance photonic system development in applications including low-energy data links, quantum optics, and neuromorphic computing.
Looking forward, we are exploring the integration of large language models and reinforcement learning techniques for automated photonic circuit design and layout optimization. These AI-driven approaches promise to accelerate the design process and discover novel architectures that could further enhance the performance of integrated photonic systems.
Hour: From 12:00h to 13:00h
Place: Seminar Room
SEMINAR: Towards an active CMOS electronics-photonics platform based on subwavelength structured devices
As Moore's Law scaling faces fundamental bottlenecks, optical communication has emerged as essential for advancing computing performance through high bandwidth and energy efficiency. Silicon photonics, compatible with CMOS manufacturing, enables on-chip optical links but requires convergence with microelectronics to realize full potential.
This work leverages advanced monolithic electronic-photonic CMOS platforms (GlobalFoundries 45CLO) to demonstrate photonic crystal (PhC) nanobeam cavities with unprecedented performance metrics. We achieved the smallest footprint, largest intrinsic quality factor exceeding 100,000, and smallest mode volume yet demonstrated in any monolithic CMOS platform—the highest quality factor among fully cladded PhC nanobeam cavities in SOI platforms.
Two critical challenges historically limited PhC cavity adoption: demanding lithography requirements and integration complications in wavelength-division multiplexing (WDM) systems due to unwanted reflections. We address the integration challenge through a novel approach using paired PhC nanobeam cavities with opposite spatial mode symmetries, creating traveling-wave-like behavior that enables seamless WDM integration without reflections.
We present the first PhC modulator demonstration in a CMOS platform, featuring sub-wavelength contacts and reflection-less architecture. This concept extends to reflectionless microring resonator units, potentially optimizing modulation efficiency for interdigitated p-n junction designs.
Finally, we demonstrate non-invasive near-field scanning optical microscopy (NSOM) characterization of photonic devices within large-scale CMOS circuits using flip-chip post-processing, providing essential tools for future high-performance photonic system development in applications including low-energy data links, quantum optics, and neuromorphic computing.
Looking forward, we are exploring the integration of large language models and reinforcement learning techniques for automated photonic circuit design and layout optimization. These AI-driven approaches promise to accelerate the design process and discover novel architectures that could further enhance the performance of integrated photonic systems.